In order to be able to make integrated circuits (ICs), such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs), such as metal-oxide-semiconductor field effect transistors (MOSFETs) and complementary metal oxide semiconductors (CMOS). Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions and operating voltages of the device while maintaining the device's electrical properties. Additionally, all dimensions of the device must be scaled simultaneously in order to optimize the electrical performance of the device.
The latest technologies for fabricating integrated circuits (or ICs) using “semiconductor-on-insulator” (or SOI) substrates have propelled semiconductor technology ahead for another generation or two of scaling. These SOI-based technologies accomplish this by balancing more expensive SOI wafer substrates with more advanced lithographic patterning tools and techniques. Integrated MOS devices based on thinner SOI substrates provide fully depleted transistor bodies, effectively eliminating undesirable floating body effects. Accordingly, there is a trend in the semiconductor industry towards ultra-thin MOS devices based upon ever-thinner SOI substrates. The term “ultra-thin SOI” denotes an active semiconductor layer of an SOI substrate having a thickness of about 20 nm or less.
Another advantage of using ultra-thin SOI substrates is that they permit the body regions of MOS devices to experience a “strain” condition such that carrier mobility (both electrons and holes) is enhanced. The thinner the active semiconductor layer of the SOI substrate becomes, the greater the strain applied to it by stressed overlayers (stress silicon nitrides being typically used in the art).
Ultra-thin SOI channel devices also provide a sharper sub-threshold slope (measure of the abruptness of the switching of the device), and better short channel effect control than semiconductor-on-insulator devices having a conventional thick channel. However, control of short channel effects with halo doping is complicated by the geometry of a conventional UTSOI device.
One solution to the aforementioned problem is to increase the dosage of the halo implant. This approach however has two main problems. The first problem with this prior art approach is that the required halo doses substantially compete with the extension implant doses and thus begin to compensate the extension implant. The second problem is that an increased halo dosage reduces the drive current of the device as well as the mobility of electrons and/or holes within the device channel.
In view of the above, there is a need for providing a new and improved method of fabricating an UTSOI device in which the short channel effects can be controlled yet avoiding/circumventing the problems with the halo implants mentioned above.